Analog architectures for neural network acceleration based on non-volatile memory: Applied Physics Reviews: Vol 7, No 3
FPGA-based Accelerators of Deep Learning Networks for Learning and Classification: A Review
Deep Neural Network ASICs The Ultimate Step-By-Step Guide eBook : Blokdyk, Gerardus: Amazon.in: Kindle Store
Why ASICs Are Becoming So Widely Popular For AI
Hardware for Deep Learning. Part 4: ASIC | by Grigory Sapunov | Intento
Intel Speeds AI Development, Deployment and Performance with New Class of AI Hardware from Cloud to Edge | Business Wire
Processing AI at the Edge: GPU, VPU, FPGA, ASIC Explained - ADLINK Blog
How to Develop High-Performance Deep Neural Network Object Detection/Recognition Applications for FPGA-based Edge Devices - Embedded Computing Design
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
Review of ASIC accelerators for deep neural network - ScienceDirect
An on-chip photonic deep neural network for image classification | Nature
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
How to develop high-performance deep neural network object detection/recognition applications for FPGA-based edge devices - Blog - Company - Aldec
Deep Learning Accelerators Foundation IP| DesignWare IP| Synopsys
Are ASIC Chips The Future of AI?
The Great Debate of AI Architecture | Engineering.com
My take on the Gartner Hype Cycle | by Jens Møllerhøj | Medium
FPGA Based Deep Learning Accelerators Take on ASICs
8-Bit Precision for Training Deep Learning Systems | IBM Research Blog
Embedded deep learning creates new possibilities across disparate industries | Vision Systems Design
Intel Unveils FPGA to Accelerate Neural Networks
Arch-Net: A Family Of Neural Networks Built With Operators To Bridge The Gap Between Computer Architecture of ASIC Chips And Neural Network Model Architectures - MarkTechPost
Google AI Blog: Chip Design with Deep Reinforcement Learning
Hardware for Deep Learning. Part 4: ASIC | by Grigory Sapunov | Intento
Space-efficient optical computing with an integrated chip diffractive neural network | Nature Communications
Processing AI at the Edge: GPU, VPU, FPGA, ASIC Explained - ADLINK Blog
